1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operable on low voltage, such as an SRAM (Static Random Access Memory).
2. Description of the Related Art
An LSI used in mobile instruments is required to reduce the power consumption to extend the battery-driven time. Lowering the supply voltage is effective to reduce the power consumption. An increase in characteristic dispersion among elements due to the progression of scaling in recent years, however, reduces the operational margin of the SRAM used in the LSI and makes it difficult to lower the operating voltage of the SRAM. The operating voltage of the SRAM defines the supply voltage of the LSI and accordingly makes it difficult to lower the supply voltage of the entire LSI. Operation of the SRAM on lower supply voltage deteriorates the write characteristic of the SRAM as a problem.
To deal with this problem, a method has been proposed, which comprises shifting one of two bit lines connected to an SRAM cell to a negative potential on writing (see K. Nii et al., “A 45-nm Single-port and Dual-port SRAM family with Robust Read/Write Stabilizing Circuitry under DVFS Environment”, 2008 Symposium on VLSI Circuits Digest of Technical Papers, P 212-213) When a boot strap circuit is used to shift one of the bit lines to the negative potential, a gate-source voltage of a transfer NMOS transistor in the SRAM cell can be boosted, thereby improving the write characteristic of the SRAM.
The use of the boot strap circuit to shift the bit line to the negative potential on writing, however, causes the following problem. The timing of shifting the bit line to the negative potential by the boot strap circuit and the level of the negative potential applied to the bit line vary depending on the capacitance of the bit line and so forth. A number of SRAMs having different word line lengths and bit line lengths are used inside the LSI. The bit lines having different bit line lengths differ from each other in bit line capacitance. Therefore, the timing of shifting the bit line to the negative potential and the level of the negative potential applied to the bit line may vary and deteriorate the characteristic of writing data to the SRAM possibly.